1. Field of the Invention
The present invention generally relates to testing methodology. More particular, the present invention relates to an apparatus for testing the crossover voltage of differential signals and its method.
2. Description of the Related Art
Traditional serial bus connections like RS-232C has at least three shortcomings: transmission speed is slow, use is complicated, and connection is limited to only a few ports. Ever since the introduction of the Universal Serial Bus (referred to as xe2x80x9cUSBxe2x80x9d hereafter) in 1996, USB has been gladly received as the newly established standard for the next generation serial bus connections with new functionality like plug and play, 12 Mbits/sec high speed transmission, support for up to 127 peripheral devices, fault-proof connector design, and low cost, etc. At present, there are a number of computer peripheral devices supporting USB standard on the market such as monitors, keyboards, mouse""s, joysticks, scanners, printers, and digital cameras, etc.
The USB bus employs a line pair for transmitting differential-type data signals. Referring to FIG. 1, the voltage waveform on data pins DP and DN of the USB bus is shown schematically, where VH and VL denote a logic-high level and a logic-low level, respectively. During a transition cycle, that is, when the voltage of the data pin DP transits from the logic-high level VH to the logic-low level VL and the voltage of the data pin DN transits from the logic-low level VL to the logic-high level VH, or vice versa, the voltage signals intersect at a point A. Usually, the voltage at the crossover point A is denominated as a crossover voltage Vcrs, where the timing placement of the crossover point A is represented by Tcrs. If the USB bus runs at a lower transmission rate, such as 1.5 Mbits/sec, the transition cycle is about 75xcx9c300 ns; if the USB bus operates at a higher transmission rate, such as 12 Mbits/sec, the transition cycle will be in the range of about 4xcx9c20 ns.
The crossover voltage Vcrs is an important parameter for evaluating USB output signals. As an example, assuming that the logic-high level VH is set to 3.3V and the logic-low level VL set to 0V, the crossover voltage Vcrs should be specified within the range of about 1.3xcx9c2.0V.
Referring to FIG. 2, a conventional apparatus for testing the crossover voltage Vcrs is schematically illustrated. As shown in the drawing, the conventional testing apparatus includes a comparator 20 configured with two input terminals connected to the data pins DP and DN, respectively. At the crossover point A, the comparator 20 generates an output signal 22 with a abrupt transition edge to trigger a voltage sampler 24. The voltage sampler 24, responsive to the abrupt transition edge, samples the voltages of the data pins DP and DN and generates the sampled value at an output terminal 26. The sampled voltage is then read by a parameter measurement unit (not shown in the drawing) of a tester.
Though the operation speed of the comparator 20 and the voltage sampler 24 is so restrictive that the sampled voltage is more or less deviated from the crossover voltage Vcrs, the sampled voltage can approximate the crossover voltage Vcrs quite well. However, the use of the comparator 20 and the voltage sampler 24 require modification of the circuitry on a load board connected between a unit-under-test (UUT) and the tester. The expense required to manufacture a resigned load board is high (up to thousands of U.S. dollars); therefore, it is not a cost-effective approach.
It is therefore an object of the present invention to provide an apparatus and a method for testing the crossover voltage of differential signals without modifying the circuitry on a load board connected between a UUT and a tester.
To attain the above-identified object, the present invention provides an apparatus for processing a signal transmitted through a pair of data lines. The apparatus has two tester channels, each of which corresponds to one of the data lines and comprises a first comparator and a second comparator and a logic circuit. The first comparator is configured with a first inverting input for receiving an upper reference and a first non-inverting input for connecting with the corresponding data line. The second comparator is configured with a second inverting input for connecting with the corresponding data line and a second non-inverting input for receiving a lower reference. The logic circuit is electrically coupled to the first comparator and the second comparator. When the signal enters a transition cycle, the first comparator and the second comparator generate logic data responsive to the upper reference and the lower reference. Then, the logic circuit compares the logic data with a logic pattern and generates a test result, accordingly.
In addition, the present invention provides a method for processing a signal transmitted through a pair of data lines. First, a voltage range defined by an upper reference and a lower reference and a logic patter are provided. Then, the signal is tested to generate logic data responsive to the voltage range. Next, the logic data are utilized to compare with the logic pattern so as to generate a test result when the signal enters a transition cycle.